Description
About the Business Unit:
Ceva is at the forefront of the Smart Edge revolution, with innovative state-of-the-art Silicon and Software solutions that enable products to Connect, Sense and Infer. Within the Wireless Internet of Things group, Ceva is offering you to be a member of our Hardware Radio team.
About the Role:
In this role you will take part in the development of the cutting-edge future communication technologies including Ultra Low power MIMO Transceivers.
You will be part of a dynamic and agile team, responsible for developing the next generations of wireless solutions for Wi-Fi, Bluetooth and UWB within the RF group located in Athens after the MEICSi acquisition of CEVA.
Responsibilities:
Own cross team planning, collaboration and coordination ensuring that team is well-aligned. Assures high quality of Analog & Mixed-Signal Layout implementations. Reports progress of layout team activities. Leads the chip level layout. Be responsible for the layout and verification (DRC, LVS, EMIR, Self-Heating) of high-end Analog/RF and mixed-signal blocks. Supports the layout team and debugging DRC/LVS/EMIR verification results. Creates layout documentation reports and participate in layout design reviews.
Requirements
- BSc, MSc in electrical engineering or equivalent degree, with 6+ years of relevant experience, OR PhD with 3+ years of experience.
- Focus in Analog/RF and Mixed-Signal Integrated Circuits
- Experience in custom layout design, with a focus on CMOS nodes 22nm and below
- Knowledge in analog layout techniques, for matching, parasitic minimizing, low power consumption
- Understanding of electromigration, coupling and crosstalk
- High level of proficiency of guard rings, DNW, trench isolation
- Knowledgeable of advanced process effects such as LOD, WPE, etc.
- Be capable to lead other layout engineers for top-level integration
- Proficiency in Cadence and Siemens DRC/LVS/Extraction and Synopsys Custom Compiler tools
- Excellent communication skills and ability to work with cross-functional teams
Advantage:
- Experience in FinFET technologies (12nm FinFET and below)
- Programming/scripting knowledge in SKILL, Perl, TCL, Shell, and/or Python is a plus
- Chip finishing/sign-off experience - a bonus